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4.9.0 beta27 / 03-08-2021

WinUAE

Accuracy

Performance

Features

WinUAE is a Commodore emulator for Windows:

  • High accuracy and compatibility for A500, A500+,  A600, A1000, A2000, CDTV

  • Good compatibility (Cycle-exact chipset emulation, CPU memory accesses are cycle-exact, CPU internal instruction execution speed is not exact) for A1200 and CD32

  • Fast CPU emulation only (chipset/chip ram CPU accesses optionally cycle-exact) for A3000, A3000T, A4000 and A4000T. To see all features, follow this link


Extension packages & Miscellaneous utilities 

  • PPC CPU core plugin, 1.5.1+ Direct3D Pixel Shader filters, Improved drive sounds, Portaudio library

  • UAEUNP 0.8 to extract Amiga based disk images and archive

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Windows: XP SP3 32-bit+

CPU: SSE2 capable

GPU: For Direct3D11 - Windows 7: SP1+

          For Direct3D9 - June 2010 DirectX 9 redistributable required

Most Recent Changes

--beta27--

Chipset updates are almost done. Optimizations added. (Which might break something that wasn't previously broken)
- Graphics glitches fixed (b26 and b25)
- Some programs (for example Wings of Death) that use OCS compatible 60Hz hack didn't have working vblank interrupt. If write to VPOSW jumped to mid last line, vblank start line check was missed.
- Added some optimizations (for example don't create new bitplane allocation table for current scanline if previous line had identical bitplane cycle sequence)
- Added bitplane/audio DMA conflict emulation that can happen in bitplane overrun situations. In this situation no DMA transfer is done (neither BPL or audio).
- Integer scale filters usually forced all scanlines to be fully redrawn, even if content didn't change.
- VPOSW fake 60Hz now uses 60Hz height if refresh rate is >=55Hz and 50Hz height if less than 55Hz. Matches 1081/1084 etc CRT behavior better.
- "Remove interlace artifacts" last line flickering fixed.



--beta26--

- Write to most programmed mode registers (ECS/AGA only) caused display emulation reinitialization, even when modified register was not in use. Now reinitialization is only done if matching BEAMCON0 bit(s) is set. Fixes BC Kid screen flashing, game updates color registers but writes too much and modifies first few programmed mode registers.
- Remove interlace artifacts option works again but is not fully functional. (last line might flicker, copper modifications are not always accurate)
- On the fly switch to subpixel mode caused hang in some situations.
- Default overscan mode had one extra pixel row and line. Overscan+ size also fixed.
- Fixed display glitches in 68020+ memory cycle exact modes (memory cycle exact only).
- Shader files are again supported in Direct3D 11 mode. FX11 moved to separate static library.



--beta25--

Last missing "weird programmed mode" feature was implemented (I hope, unless someone who does not need to be mentioned finds even more interesting programmed mode undocumented features )

- On the fly PAL/NTSC switch (VPOSW trick or BEAMCON0) incorrectly adjusted screen width in some situations. Height is now adjusted relative to total vertical lines, some games use VPOSW trick to generate 56Hz mode which was previously scaled as NTSC.
- Programmed mode (BEAMCON0 bit 7 set) with PAL/NTSC like parameters are not anymore considered as VGA-like.
- Hardwired vblank end line was 1 too late.
- Fixed repeating autoresize.
- Yet another HBLANK related undocumented feature: HBLANK start enables border. If HBLANK start is moved to visible area and bitplanes are active during HBLANK: border gets re-activated and bitplane re-starts when next BPL1DAT write happens. This probably can't be used for anything useful because display's black level detection will get confused (weird colors, wrong black level etc) if HSYNC period is not blanked.
- And another undocumented feature: if horizontal display window was closed due to HBLANK and next BPL1DAT access is close enough (and after HBLANK end in visible region, so probably can only happen in bitplane overun condition, normally shift registers empty and only background color is shown), display window opens 1.5 lores pixel early, showing previous BPL1DAT loaded pixel pattern.
- Horizontal diw now works correctly even if display horizontally "wraps around" due to (much) larger than normal HSYNC position.
- Light gun/pen fix.
- Partial fix to cycle-exact + MMU emulation (but could also happen without MMU) weird copper behavior. Internal cycle counter was not always guaranteed to be chipset cycle aligned.
- GUI lists (for example Hardware info) column DPI support.
- Fixed D3D11 OSD led crash (D3D9 worked) if display moved monitors and they had different DPI.
- Fixed RTG unexpected display size/scaling, introduces few betas ago.
- Fixed RTG related crash when switching fullscreen modes (possibly also in other modes).
- Fixed chipset emulation buffer overflow in some programmed modes, buffers need to be slightly larger now that vertical "overrun" is supported.

--beta22--

Still some custom chipset updates to do. Most likely official release will be delayed until autumn 2021.


- Copper vblank start was delayed by few cycles.
- uaegfx used unsafe (assumes unrecoverable state if invalid address) address translation function without validating the address first. Invalid VRAM address would have crashes emulated Amiga.
- "Add harddrive" tried to incorrectly guess logical geometry and didn't enable full drive mode if drive didn't already have RDB. (and it become weird and useless drive)
- Picasso96 v3.0+ uaegfx screen dragging support fixed.
- Extended window border mode joystick/mouse direction/buttons indicators fixed.
- Overscan blanking filter settings added to filter profiles.
- DMA debugger now shows AGA FMODE>0 bitplane and sprite fetch read values fully (both 32-bit and 64-bit). Previously it was always truncated to 16-bit.
- Memwatch points now fully support AGA FMODE>0 bitplane and sprite fetches.
- Memwatch log only (L) flag was not cleared when memwatch point was replaced or reset.
- Bitplane graphics wrapping around is now emulated (BPLxDAT fetch done before hsync but it is long enough to be partially visible after hsync). Normally can't happen but it can happen in bitplane DMA overrun situations or if weird programmed mode. Not fully working yet.
- Hard reset tried to free hardware emulated RTG VRAM twice causing memory corruption.

More programmed mode/normal mode special case related updates, including really weird never before used modes.Still work to do.

- Many programmed screen modes had corruption.
- Vertical now also supports wraparound (Horizontal added in b18), if vblank starts at line 0 or later (normal PAL/NTSC vblank start is last line), they will be correctly drawn after "real" last line. More lines are shown if VB starts later than normally.
- BPLCON3 EXTBLKEN (horizontal blanking) is now fully emulated and accurate. Note that ECS Denise works differently than AGA:
-* ECS Denise: ECSENA=1 + EXTBLKEN=0: blanking disabled, including vertical (except tiny blanking during hsync to keep display black level detection working), ECSENA=1 + EXTBLKEN=1 and ECSENA=0: hardwired blanking. No programmed blanking, itseems HBSTRT/HBSTOP registers don't exists in ECS Denise.
-* AGA: ECSENA=0 and ECSENA=1 + EXTBLKEN=0: hardwired blanking. ECSENA=1 + EXTBLKEN=1: HBSTRT/HBSTOP programmed horizontal blanking.
-* Note that display devices need blanked signals during part of hsync period (and vsync), it is used to set black levels, without blanking, image might become very dark or have strange colors, have strange brightness pulsing etc. This is not emulated.
- Increased internal max native display width by 2 lores pixels. ECS Denise/AGA can show 1 lores pixel more in right overscan compared to OCS. (Increased by 2 to keep display width even)
- Programmable vertical blanking is now handled accurately. VBSTOP = line when sprites are reset and first loads are done. VBSTOP+1 = first visible line. Sprites are also now emulated correctly even if VBSTRT is after vsync period. Display is now correctly blanked if vertical blank period is in visible part of display. First line of display is also adjusted depending on VBSTOP value when BEAMCON0 VARVBEN is enabled, even if other bits are not set.
- Advanced chipset "OCS H-Blank glitch" implemented (option already existed few betas ago). When enabled, first blanked line has background color visible in right border and last visible line has right border blanked. Not emulated by default because it looks really ugly and it is usually invisible when using real hardware due to overscan.
- Programmable horizontal (HSSTRT and HSSTOP) and vertical sync (VSSTRT and VSSTOP) emulation improved. Previously h/v-sync and h/v-blank was combined, now they are fully separate.

Part of below was already known previously but this time all chipset versions have been tested one by one and fully emulated now:

A1000/OCS Denise/ECS Denise last line differences:
- When A1000 Denise gets VB strobe, vertical blanking starts next line.
- When OCS Denise gets VB strobe, vertical blanking starts after 2 lines.
- When ECS Denise/AGA gets VB strobe, vertical blanking starts next line.

A1000 Agnus sends first VB strobe when current line is first line, line zero. (Which as a side-effect causes delayed vblank interrupt, interrupt is generated when line 1 starts) Other Agnus versions sends first VB strobe when current line is last line.

Bitplane DMA vertical DIW is forced closed when VB starts and sprite DMA is inhibited during all VB lines. Unless ECS/AGA and BEAMCON0 HARDDIS=1 or VARBEAMEN=1 or VARVBEN=1. (Note: DDFSTRT/STOP limits are not same, BEAMCON0 HARDDIS=1 or VARBEAMEN=1 or SHRES=1 or UHRES=1)

A1000: first blanked line is line 1. Line 0 is last visible line at the bottom of screen.
OCS Denise: first blanked line is line 1. Line 0 is last visible line at the bottom of screen. (This was not previously emulated, some programs might suddenly have different colored last line)
ECS Denise/AGA: first blanked line is line 0. Last line (312/313/262/263) is last visible line at the bottom of screen.
(Back in the CRT days last line was almost always invisible)

Normally only COLOR0 changes are visible during last line. All chipset versions have same first visible line. OCS Denise outputs 1 more visible line than ECS Denise/AGA in default PAL/NTSC modes.

Vertical blanking in this context means RGB output DAC (after Denise/Lisa) is in blanked mode. Vertical sync usually is different than vertical blanking in programmed modes.


--beta21--

Custom chipset emulation rewrite is almost done. Some tweaks and optimizations to do.

- Blitter line draw with B channel enabled supported. Flexible Zoom / Upfront uses it to load line pattern using DMA (undocumented feature, not really useful because it wastes lots of DMA time) instead of using static BLTBDAT 16-bit pattern.
- Blitter got stuck in some 68020+ CE configs.
- Copper blitter wait glitches are now accurately emulated.
- Cycle-exact mode CPU to CIA E-clock syncronization was not accurate.
- BPLxDAT CPU/copper write timing fix.
- FSINCOS native FPU mode had SIN and COS values swapped.
- If CPU reads from non-existing address space and code is executed from ROM, return all zeroes. This might not be exactly correct because it was only quickly checked on real hardware. Fixes Batman Vuelve slideshow II / Batman Group.
- A2410 works again (broke in 4300b1)


--beta20--

Custom chipset emulation rewrite is almost complete. Non-chipset emulation related bugs can be reported and they aren't ignored anymore

- Blitter internal RGA bus pipeline emulation implemented.
- When blitter was started for the first time and cycle-exact mode: blitter idle time from start of scanline to BLTSIZE write position was not emulated cycle-exactly. Almost harmless previously, now it caused visible problems with statefiles that expected blitter to steal all cycles. Very old bug.
- Copper didn't stop when both COPJMP1 and COPJMP2 was strobed without active copper DMA. (b18)
- Copper WAIT wrong special case fixed. (Hotbleeps and EyeQlazer)
- Blitter register modification while active update. (For example fixes Demo Mix 5 intro / Tommyknockers). Not 100% yet.
- AGA FMODE bit 14 bitplane scandoubling odd/even scanlines were swapped. (b18)
- Optimized mode bitplane emulation didn't do anything if scanline's bitplane pointers crossed end of chip ram. Normally never happens but really weird programs or free running bitplane pointers might not have been 100% accurately emulated ("Warning: Bad playfield pointer" message). Ancient bug with ancient comment (probably from pre-0.8 UAE) that this should be fixed someday..
- Some more UHRES parts implemented. (Yes, this is useless but cycle usage still should match real hardware if UHRES is enabled for some weird reason!)
- b18 FSINCOS update broke non-softfloat FSINCOS.


--beta19--

WARNING: don't use it you aren't sure, this is "more beta" than usually.
32-bit only. Better only have single version until things stabilize.

Bitplane max plane limit was calculated before internal aga=true variable was set. Loading AGA statefile forced OCS/ECS limits if FMODE was not updated in copper list.
- Fixed sprite glitches in some situations.
- Fixed graphics glitches if resolution was changed in horizontal blanking region.
- Different bitplane delay for odd and even planes didn't work correctly in some situations.
- Fixed memory buffer overflow when some types of file dialog was opened. (old bug)

Note: "Remove interlace artifacts" Display panel option is currently not supported. It must be disabled.
Note: Blitter cycle allocation is not yet pipelined. (Which is the real cause for 2 idle cycles after writing to BLTSIZE.) This will most likely affect copper blitter wait timing.


--beta18--

Version bumped to 4.9. (Which will become 5.0 later this year. Probably. New chipset and Voodoo 3 emulation are big enough features.)

Display emulation rewrite. Bitplane sequencer, copper (mostly) and internal pipelining is rewritten to match schematics.

NOTES
- Performance is slower when running custom chipset heavy programs. Will be improved later.
- There should be no visible differences when running "normal" programs.
- Horizontal positions shown by debugger are now shifted by 4 cycles compared to previous versions. Old versions basically used wrong origin (based on DDFSTRT immediately starting BPL DMA which was not correct). I'll write more detailed notes about internal Agnus logic later.
- Programmed mode (BEAMCON0 and friends) rewrite is still work in progress, some glitches might be visible.
- D3D9 shaders are not currently supported in D3D11 mode.

What to check


- Old bug(s) reappearing (hack removed but missing edge case wasn't reimplemented properly)
- Other bugs.
- Really bad performance. (But buy a new PC if you have something like pre-Sandy Bridge era CPU). New emulation is more complex but also some previous "lazy evaluation" optimizations might not be fully working.

- Bitplane logic internal pipeline is accurately emulated (DDFSTRT/limit check, BPRUN latch, sequencer output, RGA output latch = 4 cycle delay from DDFSTRT decision to first possible BPLxDAT slot). All known side-effects can be easily explained now. For example bitplane/copper/sprite DMA on/off mid scanline is now fully accurate (including all side-effects) with explanation that actually makes sense.
- Copper free cycle check uses pipelined bitplane allocation, copper decisions are done early (2 cycles).
- Display rendering part of emulation is now from hsync to hsync. Was previously scanline to scanline which required extra hacks to support displaying early horizontal positions in right border. All of that simply work automatically now.
- Bitplane DMA "overrun" condition special cases removed, it isn't needed anymore to handle overrun correctly. Lots of other similar hacks also become obsolete and are gone.
- Bitplane overrun new undocumented "feature": because BPL sequencer uses horizontal counter bit 0 as a clock signal, HPOS 226 to 0 transition does not increment BPL sequencer counter: same BPL cycle gets repeated.
- Lots of special case BEAMCON0 blanking/sync improvements. (Thanks Ross )
- HBSTRT/HBSTOP now supports AGA-only 140ns/70ns/35ns resolution bits.
- BPLCON3 EXTBLKEN didn't affect blanking timing if it was changed after BEAMCON0 was written to enable programmable blanking.
- Sprite emulation is now also pipelined but because most of sprite decision logic is in "STCMSD" black box, exact behavior is still not 100% known. No non-working programs known.
- DMA debugger now shows DMA cycle conflicts, top/left contains string "!<register number that conflicts>" if conflict.
- Programmed display mode vblank timing calculation fixed (usually was less than 1Hz off), also correctly uses NTSC base clock if NTSC hardware.
- Copper debugger (od) now stores also copper jumps and copper disassembler follows jumps automatically (if not after SKIP). o3 = start from vblank (COP1LC value when vblank started).
- Loading statefiles created with 4.4 or older and blitter was active when statefile was created: loading statefile corrupted memory. Old-style blitter active statefiles are not supported: blitter is restored in stopped state. I haven't yet decided if support gets re-implemented.

- Prometheus PCI config word wide access byteswap fix. Fixes Prometheus Voodoo 3 Picasso96 driver hang. Note that 8-bit has graphics corruption, driver is buggy and has off by one error when it tries render fonts (extra line of garbage) and when rendering icons (and probably other image elements), it sets host-to-screen blit height to 1 but actually keeps writing multiple lines worth of data to blitter's CPU data input register. It seems real Voodoo 3 blits all extra lines and drops the last line. Partial workaround implemented.
- Saving config file: Confirm overwrite (which is actually rename as configuration.backup) if it is read-only.
- Softfloat FMOD, FREM update. FSINCOS implemented, calculates both SIN and COS simultaneously, previously FSINCOS called SIN and COS separately. (Andreas Grabher)
- uaeserial.device CMD_WRITE with io_Length=-1 is now supported. Sends data until first zero byte.
- uaeserial.device EOFMODE support implemented.
- uaeserial.device io_ExtFlags Mark and Space parity support implemented.
- American Laser Games Platoon and Space Pirates v1.4 descrambling support added.
- Add quotes to serial, parallel and MIDI port names in config file if they begins or ends with a space. Also escape if name contains quotes.



--beta17--

  • OSD led status bar positioning fixed (b16)

  • OSD led status bar is now DPI aware. (NOTE: moving window from monitor to another monitor with different DPI does not yet work correctly)

  • BPLCON0 UHRES-bit also disables DDFSTRT/STOP limits according to Alice schematics

  • Sprites in right border were still not fully correct when they crossed "hidden" hpos=0 position. Sprite didn't disappear if start position was after hpos=0 wraparound and sprite wrap around if it started just before hpos=0 stopped too early, last few pixels were missing before start of hblank. (Thanks ross for test program)

  • One more blitter fix, last D write was done even if blit didn't have D channel enabled.

  • CPU Idle slider value added to GUI. (It was not very clear which end of slider disabled it)

  • Loading CD32 statefile with CD audio playback active: mute state was not always correctly restored.

  • Loading CD32 statefile with CD audio playback active but paused: pause state was ignored.

  • Loading CDTV statefile with CD audio playback active but paused: very short bit of audio was played before audio paused.

  • Added "Restart emulation" input target. Does same as GUI "Restart" button.

  • Reverted few b1 bitplane emulation changes. Complete rewrite will be planned for later because current emulation behavior is not really correct when compared against Alice schematics.

--

  • Hard reset leaked indirect mode allocated memory banks (outside of JIT compatible address range), for example Z3 RAM outside of partially outside of first ~2G of address space.

  • GUI misc list powerled dims option never worked, option was always cleared. (Only manual config file editing worked)

  • fix debugger command now accepts assembly syntax (for example "fi trap #0"). Only max first 3 words (if it is longer than 3 words) are used in breakpoint condition.

  • CPU% OSD leading zero removed.

  • "Blacker than black" display panel option did nothing in non-AGA modes.

  • 68060 unimplemented integer instruction mode + unimplemented instruction with -(A7)/(A7)+ addressing mode in user mode: exception stack frame was created first, then -(A7)/(A7)+ modification was incorrectly restored using supervisor stack pointer.

  • 68040/060 unimplemented FPU instructions also update FPIAR. Some invalid instructions don't but this seems to be undefined behavior. 6888x only update FPIAR if FPU exception(s) are enabled.

  • 68040/060 unimplemented FPU mode arithmetic exception fixes, all 68060 FPSP test package tests now pass. (and when run using 68040 or 6888x: test errors will match real hardware 100%)

  • Fixed FMOVEM.L #xxx,<more than one control register> disassembly.

  • Windowed mode status bar height is correctly calculated when window is moved to different DPI monitor.

  • Removed ROM scan expansion device result list. It is out of date and code was almost unmaintainable.

  • Hopefully last blitter update related fix, copper blitter waits should work correcly again. (This is a hack. Copper emulation also needs an update.)


  • PCI Virge emulation. Not much point but Virge emulation already existed, so... Not all byteswapping modes emulated, only what Mediator driver needs to work correctly. G-REX + Virge also works but 24-bit modes have some byteswap problems.

  • PCem PCI device config byte wide reads fixed (Voodoo/Virge + G-REX in CSPPC boot screen PCI list PCI device type is now shown correctly)

  • Voodoo 3 now works with G-REX CGX4 drivers.

  • G-REX didn't detect any PCI cards after FM801.

  • PCI RTG board native/RTG mode autoswitching improved.

  • Aranym JIT update missed move from FPU register to data register clamping (for example FPn -150.0 to Dn.B should become -128). Re-added.

  • Fixed FPU instruction JIT blacklist support.

  • Combitec HD 20 A/HD 40 A (not 100% sure it is exactly this model but very likely) emulation.

  • Another blitter/copper timing bug fix. (b12)

    Combitec HD 20 A/HD 40 A:

  • OMTI compatible HD controller. Usual OMTI IO offset 0x641. Base address is at $800000 + autoboot ROM at $f00000.

  • Autoboot ROM supports autoboot under KS 1.2 (seems to use same hack that other KS 1.2 autobootable HD controller use)

  • Boot ROM version string: "autoboot.device (autoboot.device 6.18 (27.8.89) , Rom_1.2, FFS, Bildchen, Search, New Boot Partition Programmiert von Bernhard Möllemann & Hartmut Sprave (C) Combitec 1988,1989"

  • Boot screen ("COMPUTER TOP EQUIPMENT COLOSSUS(R) HD-AutoBoot")


  • Fixed possible out of bounds array access when virtual mouse driver is installed.

  • Added more strict coordinate/size validation to uaegfx blitter functions.

  • JIT shift instruction fix rewrite, they still didn't work fully correctly and my tester didn't catch them because JIT uses registers differently in different use cases etc.. But it did break most Cirrus Logic based chipset Picasso96 drivers. Corrupt icons and text, at least with some Picasso96 versions. (Still need more optimal fix later)

  • Improved PCem RTG mode scanline based display update timing.

  • CyberVision64 (S3Trio64) vsync interrupt fix, could have caused stuck interrupt when monitor driver was started.

  • Hardware emulated RTG boards interlace modes fixed (again).

  • Gaps between on screen leds are now smaller.

  • FAS246 SCSI chip apparently has Features Enable always set (or bit does not exist anymore). DKB RapidFire tests if transfer count high register works (write something, read it back) and assumes it is enabled without modifying Configuration 2 Register. Rapidfire worked when it first implemented because transfer count high was not originally correctly conditionally emulated. Datasheet seems to be MIA.

  • Fixed 32-bit Chip RAM size string array out of bounds access if 768M or 1G was selected. (b11)

  • Voodoo 3 byteswapped modes Mediator PCI sound card DMA hack fix.

  • Yet another 2D/3D registers-only Voodoo 3 byteswap mode emulated. Some W3D drivers use it. (Without it nothing was rendered and log was mostly filled with "triangle_setup wrong order" messages)

  • Blitter line mode was partially broken in non-cycle exact modes and CE mode wasn't fully accurate (b12). Still some edge cases to fix.

  • DMA debugger blitter slots are now marked as BLT-x (normal), BLF-x (fill) or BLL-x (line). x = channel. RFS, DSK, AUD, SPR and BPL slots include channel numbers. (Easier to remember than xxxDAT register address numbers)


  • 68000/010 cycle-exact/prefetch: If long write access, - PCI Voodoo 3 3000 emulation from PCem.

  • Fixed existing PCI bridge emulation memory mapped space address calculations (previous PCI boards were all IO only)

  • According to Alice schematics, AGA delays blitter finished signal until last D write is done (2 cycles later, only if not line mode and D is enabled). Previous chipsets clear blitter busy (and trigger interrupt) when last D write still pending.

  • Added GVP G-Force040. Basically same as G-Force030 (same ROM, same memory config), different internal GVP hardware ID.

  • Fixed GUI debugger hang if something was selected in debugger and then focus was changed.

  • MAST Fireball DMA address pointer handling fix, some address nybbles were decoded incorrectly. (I did say it has really strange DMA address pointer setup)

  • PCem RTG boards didn't always refresh screen fully when switching modes.

  • b12 blitter fixes, start up delay was 1 cycle too long, idle cycle before final D write does not need to be free cycle.

  •  b12 blitter fixes, blitter fill mode setup missed some conditions.

  • Mainboard RAM settings disappeared in b11.

  • GD5446 (Picasso IV) blitter fix, "Invert Color Expand Source Sense" bit was not handled correctly in all blitter modes. (For example caused MUI 3.8 "REGISTER NOW" window corruption)

  • 16M VRAM (max supported) First hardware emulated board that supports full HD at 32-bit.

  • PCI board, PCI bridgeboard must be also configured.

  • BIOS ROM seems to be required (at least Mediator Voodoo Picasso96 driver reads some data from BIOS), currently must be in ROM path and named voodoo3.rom. Must be from PCI Voodoo 3 3000.

  • Native/RTG switching is implemented by checking status of SVGA screen blank bit. Might not always work correctly.

  • Hardware accelerated 3D confirmed working. (This is also partially JIT accelerated so it should be much faster than CV643D)

  • PCI to PCI DMA supported, compatible with Voodoo 3 + SB128 or FM801 sound card Mediator DMA hack.

    NOTE: At least Cirrus logic based chipsets have JIT related problems (weird looking corruption if JIT is enabeld).

Check Previous Changes